`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:25:30 10/07/2008 
// Design Name: 
// Module Name:    ALUcostum 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module flagreg #(parameter WIDTH = 16)
            (input      [WIDTH-1:0] a,
				 input		clk,
				 input		reset,
             input      C,L,F,Z,N, 
             output reg [WIDTH-1:0] flags);

		always@(posedge clk)
		begin
			if(reset)
				flags <= 16'd0;
			else
			begin
			if(C)
			flags[WIDTH-1] <= a[WIDTH-1];
			
			if(L)
			flags[WIDTH-3] <= a[WIDTH-3];

			if(F)
			flags[WIDTH-6] <= a[WIDTH-6];

			if(Z)
			flags[WIDTH-7] <= a[WIDTH-7];

			if(N)
			flags[WIDTH-8] <= a[WIDTH-8];
			
		end
		end

endmodule